Senior Verification Engineer

Job description

At the employer we provide recruitment services to top clients. We are seeking a Senior Verification Engineer to join a client team developing RISC‑V CPU cores. The role involves working within the Verification Team to ensure correctness and functionality of complex digital designs at the Register Transfer Level according to specifications, using advanced verification methodologies and tools. Responsibilities include using SystemVerilog and UVM, scripting for automation, and managing simulation and regression tools. Strong communication and teamwork are required. English C1.

Requirements

• Master or PhD
• industrial experience +8 years
• proficiency in SystemVerilog and UVM
• knowledge of scripting languages (Python, Perl, Bash, TCL) and regression tools
• experience with simulation tools
• knowledge of revision control methodology and tools (git, svn)
• experience in block level, sub‑system or top level verification
• experience with formal and dynamic verification
• strong problem‑solving skills and attention to detail
• English C1

Skills